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www.fairchildsemi.com features 0.1 hz to 250 khz dynamic range 0.01% f.s. maximum nonlinearity error 0.1hz to 10 khz 50 ppm/ c maximum gain temperature coef?ient (external reference) few external components required applications precision voltage-to-frequency converters serial transmission of analog information pulse width modulators frequency-to-voltage converters a/d converters and long term integrators signal isolation fsk modulation/demodulation frequency scaling motor speed controls phase lock loop stabilization description the 4153 sets a new standard for ease of application and high frequency performance in monolithic voltage-to- frequency converters. this voltage-to-frequency converter requires only four passive external components for precision operation, making it ideal for many low cost applications such as a/d conversion, frequency-to-voltage conversion, and serial data transmission. the improved linearity at high frequency makes it comparable to many dual slop a/d con- verters both in conversion time and accuracy, while retaining the bene?s of voltage-to-frequency conversion, i.e., serial output, cost and size. the speed accuracy and temperature performance of the 4153 is achieved by incorporating high speed ecl logic, a high gain, wide bandwidth op amp, and a buried zener reference on a single monolithic chip. RC4153 voltage-to-frequency converter www..net
product specification RC4153 2 pin assignments pin descriptions 4153-01 4153 -v s gnd 2 v ref out in o out s os1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v i c trig gnd 1 f +v +in -in v os2 v v 7.3v i one shot ref ref pin function 1-v s 2 ref gnd 3v ref output 4v out (op amp) 5i in (ref input) 6c o (pulse width) 7 trigger input 8 circuit gnd 9 frequency output (open collector) 10 +v s 11 (+) op amp input 12 (-) op amp input 13 v os trim 14 v os trim absolute maximum ratings (1) note: 1. ?bsolute maximum ratings?are those beyond which the safety of the device cannot be guaranteed. they are not meant to imply that the device should be operated at these limits. if the device is subjected to the limits in the absolute maximum rati ngs for extended periods, its reliability may be impaired. the tables of electrical characteristics provide conditions for actual device operation. thermal characteristics parameter min. typ. max. units supply voltage 18 v internal power dissipation 500 mw input voltage -v s +v s output sink current (frequency output) 20 ma storage temperature range -65 +150 c operating temperature range rv4153 -25 +80 RC4153 0 +70 c 14-lead ceramic dip 14-lead plastic dip max. junction temp +175 c +125 c max. p d t a <50 c 1042 mw 468 mw therm res q jc 60 c/w therm res q ja 120 c/w 160 c/w for t a >50 c derate at 8.33 mw/ c 6.25 mw/ c
RC4153 product specification 3 electrical characteristics (v s = 15v and t a = +25 c unless otherwise noted) parameters min. typ. max. units power supply requirements supply voltage 12 15 18 v supply current (+v s , i out = 0) +4.2 +7.5 ma (-v s , i out = 0) -7 -10 full scale frequency 250 500 khz transfer characteristics nonlinearity error voltage-to-frequency 1 0.1 hz f out 10 khz 0.002 0.01 %fs 1.0 hz f out 100 khz 0.025 0.05 %fs 5.0 hz f out 250 khz 0.06 0.1 %fs nonlinearity error frequency-to-voltage 1 0.1 hz f in 10 khz 0.002 0.01 %fs 1.0 hz f in 100 khz 0.05 0.1 %fs 5.0 hz f in 250 khz 0.07 0.12 %fs scale factor tolerance, f = 10 = khz 0.5 % change of scale factor with supply 0.008 %/v reference voltage (v ref ) 7.3 v temperature stability (0 c to 70 c) 1, 2, 3 scale factor 10 khz nominal 75 150 ppm/ c reference voltage 50 100 ppm/ c scale factor (external ref) 10 khz fs 25 50 ppm/ c scale factor (external ref) 100 khz fs 50 100 ppm/ c scale factor (external ref) 250 khz fs 100 150 ppm/ c op amp open loop output resistance 230 w short circuit current 25 ma gain bandwidth product 1 2.5 3.0 mhz slew rate 0.5 2.0 v/ m s output voltage swing (r l 3 2k) 0 to +10 -0.5 to +14.3 v input bias current 70 400 na input offset voltage (adjustable to 0) 0.5 5.0 mv input offset current 30 60 na input resistance (differential mode) 1.0 m w common mode rejection ratio 75 100 db power supply rejection ratio 70 106 db large signal voltage gain 25 350 v/mv k 1 2v ref r in c o ---------------------------------- - =
product specification RC4153 4 notes: 1. guaranteed but not tested. 2. v ref range: 6.6v v ref 8.0v. 3. over the specified operating temperature range. switched current source reference current (external reference) 1.0 ma digital input (frequency-to-voltage, pin 7) logic ? 0.5 v logic ? 2.0 v trigger current -50 m a logic output (open collector) saturation voltage (pin 9) i sink = 4 ma 0.15 0.4 v i sink = 10 ma 0.4 1.0 v i leak (off state) 150 na parameters min. typ. max. units
RC4153 product specification 5 typical performance characteristics t a ( ? c) 10 khz full scale drift output frequency vs. temperature 250 khz full scale drift output frequency vs. temperature 250 khz frequency-to-voltage nonlinearity vs. input voltage 250 khz voltage-to-frequency nonlinearity vs. input voltage 250 khz full scale peak nonlinearity vs. scale factor f out (khz) -60 -40 -20 0 +20 +40 +60 +80 +100 +120 10.06 10.03 10 9.97 9.94 9.91 t a ( ? c) f out (khz) -60 -40 -20 0 +20 +40 +60 +80 +100 +120 250.8 250.4 250.0 249.6 249.2 248.8 nl (% error) v in (v) 0.08 0.04 0 -0.04 -0.08 -0.12 1 2 345678910 0 nl (% error) f in (khz) 0.09 0.06 0.03 0 -0.03 25 50 75 100 125 150 175 200 225 -0.06 250 0 4153-02 k (khz) nl (absolute % error) 0 30 60 0 120 150 180 210 240 0.10 0.08 0.06 0.04 0.02 0 270 f-to-v v-to-f
product specification RC4153 6 typical performance characteristics nl (% error) v in (v) 10 khz voltage-to-frequency nonlinearity vs. input voltage 10 khz frequency-to-voltage nonlinearity vs. input frequency 50 khz voltage-to-frequency nonlinearity vs. input voltage 50 khz frequency-to-voltage nonlinearity vs. input frequency 100 khz voltage-to-frequency nonlinearity vs. input voltage 100 khz frequency-to-voltage nonlinearity vs. input frequency 0.004 0.002 0 -0.002 -0.004 -0.006 1 2 3456789 10 0 nl (% error) f in (khz) 0.004 0.002 0 -0.002 -0.004 -0.006 1 2 3456789 10 0 nl (% error) v in (v) 0.01 0.05 0 -0.005 -0.01 -0.015 1 2 345678910 0 nl (% error) f in (khz) 0.008 0.004 0 -0.004 -0.008 -0.012 5 10 15 25 30 35 40 45 20 50 0 nl (% error) 0.04 0.02 0 -0.02 -0.04 -0.06 v in (v) 1 2 345678910 0 4153-03 nl (% error) f in (khz) 0.04 0.02 0 -0.02 -0.04 -0.06 10 20 30 40 50 60 70 80 90 100 0
RC4153 product specification 7 typical application circuits figure 1. voltage-to-frequency converter minimum circuit figure 2. frequency-to-voltage converter 4153-04 4153 -v s gnd 2 v ref out in o out s 1 2 3 4 5 6 78 9 10 11 12 13 14 v v c trig gnd 1 f +v * +in -in v 7.3v i one shot ref ref v os1 f out r 5.1k l t t o c v in c = 30 c io full scale c c r 10 khz 0.1 f 3300 pf 20k 50 khz 0.02 f 680 pf 20k 100 khz 4300 pf 330 pf 20k 250 khz 1000 pf 130 pf 20k io in m m t = t = 1.5 x 10 c c 4 o o 1 f 5 x 10 f (max) out out -5 ** for bipolar input f = out in ref ref in o v r + v r 2r r v c in s ref f = (v = 7.3v) * v must be thoroughly decoupled. ** for bipolar input. resistance in ohms unless otherwise specified. out ref in in s ref v 2v r c o r in r ** s v os2 4153-05 4153 -v * s gnd 2 v ref out in o out s 1 2 3 4 5 6 78 9 10 11 12 13 14 v v c trig gnd 1 f +v +in -in vos v 7.3v i one shot ref ref -v * s f in (0 -10 khz) c 0.002 pf in r1 10k +v * s c 3.3 nf o r2 5.1k voltage output c i r 10k v = 2v r c f c 5 x 10 f (max) o ref o in out v os1 v os2 5k 18.7k r b -5 f out ** r = 5.1k** l +v s r 20k b' c 0.01 f (cer disk) b' v must be thoroughly decoupled. ** optional. resistance in ohms unless otherwise specified. s full scale adjust full scale c c r 10 khz 10 f 3300 pf 20k 50 khz 2 f 330 pf 40k 100 khz 1 f 150 pf 43k 250 khz 0.2 f 60 pf 39k io m m m m b v = t = ripple recovery 2v c (1 - 1.5 x 10 c f ) c 1.36 x 10 c c r f 4 i o b in i o o in 4 ref in b *
product specification RC4153 8 typical application circuit (continued) figure 3. voltage-to-frequency converter with offset and gain adjusts 4153-06 4153 -v s gnd 2 v ref out in o out s 1 2 3 4 5 6 78 9 10 11 12 13 14 v i c trig gnd 1 f +v * +in -in v 7.3v i one shot ref ref v os1 r os 10k zero adj. v os2 r 5.1k l o c c 0.01 f (mylar) i full scale c c r 10 khz 0.1 f 3300 pf 20k 50 khz 0.02 f 680 pf 20k 100 khz 4300 pf 330 pf 20k 250 khz 1000 pf 130 pf 20k i o in m m o 5 x 10 f (max) out -5 f = * v must be thoroughly decoupled. resistance in ohms unless otherwise specified. out ref in in s v 2v r c o r full scale adjust in v in (0 to 10v) r 20k b' frequency output c 0.01 f (cer disk) m b' c -v * s m
RC4153 product specification 9 voltage reference 7.3v switched current source r in v in 0 to 10v a i o ut c (timing) o c b i c trigger +v s ext load e open collector output d one shot integrator 4153-07 principles of operation the 4153 consists of several functional blocks which provide either voltage-to-frequency or frequency-to-voltage conver- sion, depending on how they are connected. the operation is best understood by examining the block diagram as it is pow- ered in a voltage-to-frequency mode (figure 4). when power is ?st applied, all capacitors are discharged. the input current, v in /r in , causes c i to charge, and point c will try to ramp down. the trigger threshold of the one-shot is approximately +1.3v, and if the integrator output is less than +1.3v, the one-shot will ?e and pulse the open collec- tor output e and the switched current source a (see figures 4 and 5). because the point c is less than +1.3v, the one-shot ?es, and the switched current source delivers a negative current pulse to the integrator. this causes c in to charge in the opposite direction, and point c will ramp up until the end of the one-shot pulse. at that time, the positive current v in /r in will again make point c ramp down until the trigger threshold is reached. when power is applied, the one-shot will continuously ?e until the integrator output exceeds the trigger threshold. once this is reached, the one-shot will ?e as needed to keep the integrator output above the trigger threshold. if v in is increased, the slope of the downward ramp increases, and the one-shot will ?e more often in order to keep the integrator output high. since the one-shot ?ing frequency is the same as the open collector output frequency, any increase in v in will cause an increase in f out . this relationship is very linear because the amount of charge in each i out pulse is carefully de?ed, both in magnitude and duration. the dura- tion of the pulse is set by the timing capacitor c o (point d). this feedback system is called a charge-balanced loop. the scale factor k (the number of pulses per second or a speci?d v in ), is adjusted by changing either r in and there- fore i in , or by changing the amount of charge in each i out pulse. since the magnitude of i out is ?ed at 1 milliamp, the way to change the amount of charge is by adjusting the one- shot duration set by c o (i out may be adjusted by changing v ref ). the accuracy of the relationship between v in and f out is affected by three major sources of error: temperature drift, nonlinearity and offset. the total temperature drift is the sum of the individual drift of the components that make up the system. the greatest source of drift in a typical application is in the timing capacitor, c o . low temperature coef?ient capacitors, such as silver mica and polystyrene, should be measured for drift using a capacitance meter. experimentation has shown that the lowest tempcos are achieved by wiring a parallel capaci- tor composed of 70% silver mica and 30% polystyrene. the reference on the chip can be replaced by an external reference with much tighter drift speci?ations, such as an lm199. the 199s 6.9v output is close to the 4153s 7.3v output, and has less than 10 ppm/ c drift. nonlinearity is primarily caused by changes in the precise amount of charge in each i out pulse. as frequency increases, internal stray capacitances and switching problems change the width and amplitude of the i out pulses, causing a nonlinear relationship between v in and f out . figure 4. voltage-to-frequency block diagram figure 5. voltage-to-frequency timing waveforms v out +5v +10v 0 a -i b c in d e switched current source output -1.0 ma switched current source logic (internal) integrator output v +1.3v trigger ~ ~ -0.65v one shot timing (c ) t = 1.5 x 10 c -4.1v -v s logic output -0.2v f = v 2v r c o in ref o in 4 o o 4153-08
product specification RC4153 10 f in 100 w 100k comparator with hysteresis c a s a b i o out+ +v r r input coupling 13 1 10 14 7 3 5 2 8 9 4153 -15v +15v 4 12 11 6 r r v c c i i 4153-09 -in +in f out o c gnd2 gnd1 i in v ref trig v os1 v os2 -v s +v s v out for this reason, the scale factor you choose should be below 1 khz/v or as low as the acquisition time of your system will allow. nonlinearity is also affected by the rate of c i to c o . less error can be achieved by increasing the value of c i , but this affects response time and temperature drift. optimum value for c i and c o are shown in the tables in figures 1, 2, and 3. these values represent the best compromise of nonlinearity and temperature drift. polypropylene, mylar or polystyrene capacitors should be used for c i . the accuracy at low input voltages is limited by the offset and v os drift of the op amp. to improve this condition, an offset adjust is provided. once your system is running, it may be calibrated as follows: apply a measured full scale input voltage and adjust r in until the scale factor is correct. for precise applications, trimming by soldering metal ?m resistors in parallel is recommended instead of trimpots, which have bad tempcos and are easily taken out of adjustment by mechanical shock. after the scale factor is calibrated, apply a known small input voltage (approximately 10 mv) and adjust the op amp offset until the output frequency equals the input multiplied by the scale factor. the output e consists of a series of negative going pulses with a pulse width equal to the one-shot time. the open collector pull-up resistor may be connected to a different supply (such as 5v for ttl) as long a it does not exceed the value of +v s applied to pin 10. the load current should be kept below 10 ma in order to minimize strain on the device. pins 2 and 8 must be grounded in all applications, even if the open collector transistor is not used. figure 6 shows the complete circuit for a precision frequency-to-voltage converter. the circuit converts an input frequency to a proportional voltage by integrating the switched current source output. as the input frequency increases, the number of i out pulses delivered to the integra- tor increases, thus increasing the average output voltage. depending on the time constant of the integrator, there will be some ripple on the output. the output may be further ?tered, but this will reduce the response time. a second order ?ter will decrease ripple and improve response time. the input waveform must meet three conditions for proper frequency-to-voltage operation. first, it must have suf?ient amplitude and offset to swing above and below the 1.3v trigger threshold (see figure 6 for an example of ac coupling and offset bias.) second, it must be a fast slewing waveform having a quick rise time. a comparator may be used to square it up. finally, the input pulse width must not exceed the one-shot time, in order to avoid retriggering the one-shot (ac couple the input). capacitive coupling between the trigger input and the timing capacitor pin may occur if the input waveform is a square- wave or the input has a short period. this can cause gross nonlinearity due to changes in the one-shot timing waveform (see figure 7). this problem can be avoided by keeping the value of c o small, and thereby keeping the timing period less than the input waveform period. figure 6. frequency-to-voltage precision converter
RC4153 product specification 11 timing waveform on c input frequency input frequency timing waveform on c gitch proper operation improper operation 4153-10 o o 4153-11 t th o b to switched current source trig reset q r-s latch c d c i v comparator ramp gen detailed circuit operation the circuit consists of a buried zener reference (breakdown occurs below the surface of the die, reducing noise and contamination), a high speed one-shot, a high speed switched precision voltage-to-current converter and an open-collector output transistor. figure 8 shows a block diagram of the high speed one-shot and figure 9 shows the monolithic implementation. a trigger pulse sets the r-s latch, which lets c o charge from i t . when the voltage on c o exceeds v th . the comparator resets the latch and discharges c o . looking at the detailed schematic, a positive trigger voltage turns on q5, turns off q4, and turns on q3. q3 provides more drive to q5 keeping it on and latching the base of q11 low. this turns on the switched current source and turns off q1, allowing c o to charge in a negative direction. when the voltage on c o exceeds v th , q13s collector pulls q3s base down, resetting the latch, turning off the switched current source and discharging c o through q1. note that all of the transistors in the signal path are npns, and that the voltage swings are minimized ecl fashion to reduce delays. minimum delay means minimum drift of the resultant vfc scale factor at high frequency. figure 7. frequency-to-voltage timing waveforms figure 8. one-shot block diagram
product specification RC4153 12 r60 q35 q36 -v s +7.3v ref a b switched current source output from one shot 4153-13 v gnd trigger c d1 q2 d2 q4 q5 q3 -v s r-s latch comparator ramp generator i 1.0 ma i q7 q8 q11 q12 d3 q6 (b) q10 v th i out q13 q14 d q1 c o t 4153-12 i the switched current source is shown as a block diagram in figure 10 and detailed in figure 11. the summing node (+ input of the op amp) is held at 0v by the ampli?r feed- back, causing v ref to be applied across r60. this current (v ref /r60), minus the small ampli?r bias current, ?ws through q35. q35 develops a v be dependent on that current. this v be is developed across q36. since q35 and q36 are equal in area, the currents are equal. the mirrored current is switched by the one-shot output. the detail schematic shows the ampli?r and load (q21 through q34), the mirror transistors (q35, q36) and the dif- ferential switching transistors (q7, q8). the ampli?r uses a complementary paraphase input composed of q21 through q26 with a current mirror formed by q27 through q30, which converts from differential to single-ended output. level-shift diodes q32 and q34 and emitter follower q31 bootstrap the emitters of the mirror devices q29 and q30 to increase gain and lower input offsets, which would otherwise be caused by unbalanced collector voltages on q23 and q26. figure 9. one-shot (detail) figure 10. switched current source block diagram
RC4153 product specification 13 4153-14 ref i to collector of q11 q8 b q7 q36 q35 r4 39.2 k r3 39.2 k q32 r2 56.2 k q34 +v s to v q26 c1 q38 r60 v in switched current output source a q22 q21 to +v s q25 q24 q27 q28 q31 q30 r43 56.2 k r1 34 k to bias network q1 q29 q23 r46 b s -v w w w w w matching emitter currents in q35 and q36 are assured by degeneration resistors r3 and r4. the differential switch allows the current source to remain active continuously, shunting to ground in the off state. this helps stabilize the output, and again, npns reduce switching time, timing errors, and most important, drift of timing errors over tem- perature. figure 11. switched current source (detail)
product specification RC4153 14 schematic diagram offset adjust c i to -in pulse output r l f out c o v os1 v os2 v out trig r18 one shot rm4153 r b v in r b1 gnd1 gnd2 v ref i in -v s vref 1 2 r59 -in +in +v s q75 q76 q77 q73 q74 r c3 15 pf q72 r44 200 r45 5.11 d71 6.3v gnd2 i in -v s r1 3.4k q11 q9 r43 40.2 q7 q3 q4 q5 q1 r46 6.8k q2 q6 c1 25 pf n+ r11 51.1 r14 5.92 q30 q29 r59 0.15 q80 q81 q82 q83 q97 +v s l o v out q66 npn r13 10 q38 q39 q67 q33 r17 20 d68 6.3 r19 5.11 q36 q35 q34 r16 20 q42 q45 r25 8.25 q46 r23 8.25 q44 r24 8.25 q47 r22 8.25 q48 r21 8.25 q50 r27 3.92 q49 r26 8.25 q51 r28 8.25 q52 r23 8.25 q53 r35 8.25 r38 24.3 r36 4.82 q31 q32 r39 9.6 +v s gnd1 r48 4.8k q78 d89 q97 q98 q84 q94 q59 q40 q41 d70 6.3 q64 q65 q43 r29 12 r30 12 r32 0.511 r32 .511 q63 q54 q57 q58 q56 q55 4153-15 q61 q62 q60 trig r34 20 c o r20 15 d69 6.3 r42 30 q24 q25 q27 r8 5.11 r12 8.25 r7 20 d28 6.3 d18 5.5 r9 20 c4 15 pf q23 q17 q16 q18 r5 40.2 r4 3.92 r3 3.92 r2 56.2 q14 q12 q15 q8 q13 q10 +v s v ref v os1 -in +in v os2 q92 q93 q95 q96 r56 0.02 r57 0.02 gnd1 r52 22k r53 0.10 q90 r55 500 c2 13 pf al d88 r51 18k q87 q85 q91 q86 r49 1k r50 1k q28 q20 q21 q22 q26 r10 47.5 r59 6.8 notes: all resistor values are in k w al = aluminum r54 0.03 q79 n+ +v s r18 13.6 r37 3.65 r6 20
RC4153 product specification 15 notes:
product specification RC4153 6/25/98 0.0m 002 stock#ds30004153 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ordering information notes: n = 14-lead plastic dip part number package operating temperature range RC4153n n 0 c to +70 c rv4153n n -25 c to 80 c

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